Image sensor with time overlapping image output

ABSTRACT

An image sensor system with an image sensor that generates a first image and a second image. The first and second images are transmitted to a processor in a time overlapping manner. By way of example, the images may be transferred to the processor in an interleaving manner or provided on separate dedicated busses.

REFERENCE TO CROSS RELATED APPLICATION

This application is a continuation-in-part of application Ser. No.10/236,515 filed on Sep. 6, 2002; that claims priority to provisionalapplication No. 60/345,672 filed on Jan. 5, 2002, and provisionalapplication No. 60/358,611 filed on Feb. 21, 2002, this application alsoclaims priority under 35 U.S.C §119(e) to provisional application No.60/455,436 filed on Mar. 15, 2003.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The subject matter disclosed generally relates to the field ofsemiconductor image sensors.

2. Background Information

Photographic equipment such as digital cameras and digital camcorderscontain electronic image sensors that capture light for processing intoa still or video image, respectively. There are two primary types ofelectronic image sensors, charge coupled devices (CCDs) andcomplimentary metal oxide semiconductor (CMOS) sensors. CCD imagesensors have relatively high signal to noise ratios (SNR) that providequality images. Additionally, CCDs can be fabricated to have pixelarrays that are relatively small while conforming with most camera andvideo resolution requirements. A pixel is the smallest discrete elementof an image. For these reasons, CCDs are used in most commerciallyavailable cameras and camcorders.

CMOS sensors are faster and consume less power than CCD devices.Additionally, CMOS fabrication processes are used to make many types ofintegrated circuits. Consequently, there is a greater abundance ofmanufacturing capacity for CMOS sensors than CCD sensors.

To date there has not been developed a CMOS sensor that has the same SNRand pixel pitch requirements as commercially available CCD sensors.Pixel pitch is the space between the centers of adjacent pixels. Itwould be desirable to provide a CMOS sensor that has relatively high SNRwhile providing a commercially acceptable pixel pitch.

The image sensor is typically connected to an external processor andexternal memory. The external memory stores data from the image sensor.The processor processes the stored data. To improve picture quality itis sometimes desirable to capture two different images of the samepicture. With CCD sensors there is an inherent delay between capturingthe first image and capturing the second image. The image may moveduring this delay. This image movement may degrade the quality of theresultant picture. It would be desirable to decrease the time requiredto capture and transmit images from the pixel array. It would also bedesirable to provide a low noise, high speed, high resolution imagesensor that can utilize external memory.

BRIEF SUMMARY OF THE INVENTION

An image sensor system that includes an image sensor that transmits afirst image and a second image to a processor in a time overlappingmanner.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic of an embodiment of an image sensor;

FIG. 2 is an illustration of a method for storing pixel data in anexternal memory for a still image;

FIG. 3 is an illustration of a method for retrieving and combining pixeldata for a still image;

FIG. 4 is an illustration of an alternate method for retrieving andcombining pixel data;

FIG. 5 is an illustration of alternate method for retrieving andcombining pixel data;

FIG. 6 is an illustration of alternate method for retrieving andcombining pixel data;

FIG. 7 is an illustration of alternate method for retrieving andcombining pixel data;

FIG. 8 is an illustration showing a method for storing and combiningpixel data for a video image;

FIG. 9 is another illustration showing the method for storing andcombining pixel data for a video image;

FIG. 10 is an illustration showing a method for converting theresolution of pixel data;

FIG. 11 is an illustration showing an alternate method for convertingthe resolution of the pixel data;

FIG. 12 is an illustration showing an alternate method for convertingthe resolution of the pixel data;

FIG. 13 is a schematic of an embodiment of a pixel of the image sensor;

FIG. 14 is a schematic of an embodiment of a light reader circuit of theimage sensor;

FIG. 15 is a flowchart for a first mode of operation of the imagesensor;

FIG. 16 is a timing diagram for the first mode of operation of the imagesensor;

FIG. 17 is a diagram showing the levels of a signal across a photodiodeof a pixel;

FIG. 18 is a schematic for a logic circuit for generating the timingdiagrams of FIG. 16;

FIG. 19 is a schematic of a logic circuit for generating a RST signalfor a row of pixels;

FIG. 20 is a timing diagram for the logic circuit shown in FIG. 19;

FIG. 21 is a flowchart showing a second mode of operation of the imagesensor;

FIG. 22 is a timing diagram for the second mode of operation of theimage sensor;

FIG. 23 a is a schematic of an alternate embodiment of an image sensorsystem;

FIG. 23 b is a schematic of an alternate embodiment of an image sensorsystem;

FIG. 24 is a schematic of an alternate embodiment of an image sensorsystem;

FIG. 25 is a schematic of an alternate embodiment of an image sensorsystem;

FIG. 26 is a schematic of an alternate embodiment of an externalprocessor;

FIG. 27 is a schematic of an alternate embodiment of an image sensorsystem;

FIG. 28 is a schematic of an embodiment of a processor for the processorshown in FIG. 27;

FIG. 29 is a schematic of an embodiment of a DMA controller for theprocessor shown in FIG. 28.

DETAILED DESCRIPTION

Disclosed is an image sensor system with an image sensor that generatesa first image and a second image. The first and second images aretransmitted to a processor in a time overlapping manner. By way ofexample, the images may be transferred to the processor in aninterleaving manner or provided on separate dedicated busses.

The entire image sensor is preferably constructed with CMOS fabricationprocesses and circuits. The CMOS image sensor has the characteristics ofbeing high speed, low power consumption, small pixel pitch and a highSNR.

Referring to the drawings more particularly by reference numbers, FIG. 1shows an image sensor 10. The image sensor 10 includes a pixel array 12that contains a plurality of individual photodetecting pixels 14. Thepixels 14 are arranged in a two-dimensional array of rows and columns.

The pixel array 12 is coupled to a light reader circuit 16 by a bus 18and to a row decoder 20 by control lines 22. The row decoder 20 canselect an individual row of the pixel array 12. The light reader 16 canthen read specific discrete columns within the selected row. Together,the row decoder 20 and light reader 16 allow for the reading of anindividual pixel 14 in the array 12.

The light reader 16 may be coupled to an analog to digital converter 24(ADC) by output line(s) 26. The ADC 24 generates a digital bit stringthat corresponds to the amplitude of the signal provided by the lightreader 16 and the selected pixels 14.

The ADC 24 is coupled to a pair of first image buffers 28 and 30, and apair of second image buffers 32 and 34 by lines 36 and switches 38, 40and 42. The first image buffers 28 and 30 are coupled to a memorycontroller 44 by lines 46 and a switch 48. The memory controller 44 canmore generally be referred to as a data interface. The second imagebuffers 32 and 34 are coupled to a data combiner 50 by lines 52 and aswitch 54. The memory controller 44 and data combiner 50 are connectedto a read back buffer 56 by lines 58 and 60, respectively. The output ofthe read back buffer 56 is connected to the controller 44 by line 62.The data combiner 50 is connected to the memory controller 44 by line64. Additionally, the controller 44 is connected to the ADC 24 by line66.

The memory controller 44 is coupled to an external bus 68 by acontroller bus 70. The external bus 68 is coupled to an externalprocessor 72 and external memory 74. The bus 70, processor 72 and memory74 are typically found in existing digital cameras, cameras and cellphones.

To capture a still picture image, the light reader 16 retrieves a firstimage of the picture from the pixel array 12 line by line. The switch 38is in a state that connects the ADC 24 to the first image buffers 28 and30. Switches 40 and 48 are set so that data is entering one buffer 28 or30 and being retrieved from the other buffer 30 or 28 by the memorycontroller 44. For example, the second line of the pixel may be storedin buffer 30 while the first line of pixel data is being retrieved frombuffer 28 by the memory controller 44 and stored in the external memory74.

When the first line of the second image of the picture is available theswitch 38 is selected to alternately store first image data and secondimage data in the first 28 and 30, and second 32 and 34 image buffers,respectively. Switches 48 and 54 may be selected to alternatively storefirst and second image data into the external memory 74 in aninterleaving manner. This process is depicted in FIG. 2.

There are multiple methods for retrieving and combining the first andsecond image data. As shown in FIG. 3, in one method each line of thefirst and second images are retrieved from the external memory 74 at thememory data rate, stored in the read back buffer 56, combined in thedata combiner 50 and transmitted to the processor 72 at the processordata rate. Alternatively, the first and second images may be stored inthe read back buffer 56 and then provided to the processor 72 in aninterleaving or concatenating manner without combining the images in thecombiner 50. This technique allows the processor 72 to process the datamanner in different ways.

FIG. 4 shows an alternative method wherein the external processor 72combines the pixel data. A line of the first image is retrieved from theexternal memory 74 and stored in the read back buffer 56 at the memorydata rate and then transferred to the external processor 72 at theprocessor data rate. A line of the second image is then retrieved fromthe external memory 74, stored in the read back buffer 56, andtransferred to the external processor 72. This sequence continues foreach line of the first and second images. Alternatively, the entirefirst image may be retrieved from the external memory 74, stored in theread back buffer 56 and transferred to the external processor 72, oneline at a time, as shown in FIG. 5. Each line of the second image isthen retrieved from the external memory 74, stored in the read backbuffer 56 and transferred to the external processor 72.

In the event the processor data rate is the same as the memory data ratethe processor 72 may directly retrieve the pixel data rate from theexternal memory 74 in either an interleaving or concatenating manner asshown in FIGS. 6 and 7, respectively. For all of the techniquesdescribed, the memory controller 44 provides arbitration for datatransfer between the image sensor 10, the processor 72 and memory 74. Toreduce noise in the image sensor 10, the controller 44 preferablytransfers data when the light reader 16 is not retrieving outputsignals.

To capture a video picture, the lines of pixel data of the first imageof the picture may be stored in the external memory 74. When the firstline of the second image of the picture is available, the first line ofthe first image is retrieved from memory 74 at the memory data rate andcombined in the data combiner 50 as shown in FIGS. 8 and 9. The combineddata is transferred to the external processor 72 at the processor datarate. As shown in FIG. 9, the external memory is both outputting andinputting lines of pixel data from the first image at the memory datarate.

For video capture the buffers 28, 30, 32 and 34 may perform a resolutionconversion of the incoming pixel data. There are two common videostandards NTSC and PAL. NTSC requires 480 horizontal lines. PAL requires590 horizontal lines. To provide high still image resolution the pixelarray 12 may contain up to 1500 horizontal lines. The image sensorconverts the output data into a standard format. Converting on board theimage sensor reduces the overhead on the processor 72.

FIG. 10 shows a technique for converting the resolution and reducing theamount of data. Reducing data lowers the noise and power consumption ofthe image sensor. Additionally, lower data reduces the memoryrequirements of the external memory. The first method reduces 4contiguous columns and four contiguous rows of pixels to 2 columns and 2rows of pixels. The pixel array 12 includes a 4 by 4 pixel groupcontaining red (R), green (G) and blue (B) pixels arranged in a Bayerpattern. The 4 by 4 array is reduced to a 2 by 2 array in accordancewith the following equations:

R=¼*(R ₁ +R ₂ +R ₃ +R ₄)  (1)

B=¼*(B ₁ +B ₂ +B ₃ +B ₄)  (2)

G _(B)=½*(G ₁ +G ₂)  (3)

G _(R)=½*(G ₃ +G ₄)  (4)

The net effect is a 75% reduction in the data rate, arranged in a Bayerpattern.

FIG. 11 shows an alternative method for resolution conversion. Thesecond technique provides a 4:2:0 encoding that is compatible withMPEG-2. The conversion is performed using the following equations:

R=¼*(R ₁ +R ₂ +R ₃ +R ₄)  (5)

B=¼*(B ₁ +B ₂ +B ₃ +B ₄)  (6)

G _(B)=½*(G ₁ +G ₂)  (7)

G _(R)=½*(G ₃ +G ₄)  (8)

G _(BB)=½*(G ₅ +G ₆)  (9)

G _(RR)=½*(G ₇ +G ₈)  (10)

The net effect is a 62.5% reduction in the data rate.

FIG. 12 shows yet another alternative resolution conversion method. Thethird method provides a 4:2:2 encoding technique using the followingequations:

G ₁₂=½*(G ₁ +G ₂)  (11)

G ₃₄=½*(G ₃ +G ₄)  (12)

G ₅₆=½*(G ₅ +G ₆)  (13)

G ₇₈=½*(G ₇ +G ₈)  (14)

R ₁₂=½*(R ₁ +R ₂)  (15)

R ₃₄=½*(R ₃ +R ₄)  (16)

B ₁₂=½*(B ₁ +B ₂)  (17)

B ₃₄=½*(B ₃ +B ₄)  (18)

The net effect is a 50% reduction in the data rate.

To conserve energy the memory controller 44 may power down the externalmemory 74 when memory is not receiving or transmitting data. To achievethis function the controller 44 may have a power control pin 76connected to the CKE pin of a SDRAM (see FIG. 1).

FIG. 13 shows an embodiment of a cell structure for a pixel 14 of thepixel array 12. The pixel 14 may contain a photodetector 100. By way ofexample, the photodetector 100 may be a photodiode. The photodetector100 may be connected to a reset transistor 112. The photodetector 100may also be coupled to a select transistor 114 through a level shiftingtransistor 116. The transistors 112, 114 and 116 may be field effecttransistors (FETs).

The gate of reset transistor 112 may be connected to a RST line 118. Thedrain node of the transistor 112 may be connected to IN line 120. Thegate of select transistor 114 may be connected to a SEL line 122. Thesource node of transistor 114 may be connected to an OUT line 124. TheRST 118 and SEL lines 122 may be common for an entire row of pixels inthe pixel array 12. Likewise, the IN 120 and OUT 124 lines may be commonfor an entire column of pixels in the pixel array 12. The RST line 118and SEL line 122 are connected to the row decoder 20 and are part of thecontrol lines 22.

FIG. 14 shows an embodiment of a light reader circuit 16. The lightreader 16 may include a plurality of double sampling capacitor circuits150 each connected to an OUT line 124 of the pixel array 12. Each doublesampling circuit 150 may include a first capacitor 152 and a secondcapacitor 154. The first capacitor 152 is coupled to the OUT line 124and ground GND1 156 by switches 158 and 160, respectively. The secondcapacitor 154 is coupled to the OUT line 124 and ground GND1 by switches162 and 164, respectively. Switches 158 and 160 are controlled by acontrol line SAM1 166. Switches 162 and 164 are controlled by a controlline SAM2 168. The capacitors 152 and 154 can be connected together toperform a voltage subtraction by closing switch 170. The switch 170 iscontrolled by a control line SUB 172.

The double sampling circuits 150 are connected to an operationalamplifier 180 by a plurality of first switches 182 and a plurality ofsecond switches 184. The amplifier 180 has a negative terminal − coupledto the first capacitors 152 by the first switches 182 and a positiveterminal + coupled to the second capacitors 154 by the second switches184. The operational amplifier 180 has a positive output + connected toan output line OP 188 and a negative output − connected to an outputline OM 186. The output lines 186 and 188 are connected to the ADC 24(see FIG. 1).

The operational amplifier 180 provides an amplified signal that is thedifference between the voltage stored in the first capacitor 152 and thevoltage stored in the second capacitor 154 of a sampling circuit 150connected to the amplifier 180. The gain of the amplifier 180 can bevaried by adjusting the variable capacitors 190. The variable capacitors190 may be discharged by closing a pair of switches 192. The switches192 may be connected to a corresponding control line (not shown).Although a single amplifier is shown and described, it is to beunderstood that more than one amplifier can be used in the light readercircuit 16.

FIGS. 15 and 16 show an operation of the image sensor 10 in a first modealso referred to as a low noise mode. In process block 300 a referencesignal is written into each pixel 14 of the pixel array and then a firstreference output signal is stored in the light reader 16. Referring toFIGS. 13 and 16, this can be accomplished by switching the RST 118 andIN 120 lines from a low voltage to a high voltage to turn on transistor112. The RST line 118 is driven high for an entire row. IN line 120 isdriven high for an entire column. In the preferred embodiment, RST line118 is first driven high while the IN line 120 is initially low.

The RST line 118 may be connected to a tri-state buffer (not shown) thatis switched to a tri-state when the IN line 120 is switched to a highstate. This allows the gate voltage to float to a value that is higherthan the voltage on the IN line 120. This causes the transistor 112 toenter the triode region. In the triode region the voltage across thephotodiode 100 is approximately the same as the voltage on the IN line120. Generating a higher gate voltage allows the photodetector to bereset at a level close to Vdd. CMOS sensors of the prior art reset thephotodetector to a level of Vdd-Vgs, where Vgs can be up to 1 V.

The SEL line 122 is also switched to a high voltage level which turns ontransistor 114. The voltage of the photodiode 100 is provided to the OUTline 124 through level shifter transistor 116 and select transistor 114.The SAM1 control line 166 of the light reader 16 (see FIG. 14) isselected so that the voltage on the OUT line 124 is stored in the firstcapacitor 152.

Referring to FIG. 15, in process block 302 the pixels of the pixel arrayare then reset and reset output signals are then stored in the lightreader 16. Referring to FIGS. 13 and 16 this can be accomplished bydriving the RST line 118 low to turn off the transistor 112 and resetthe pixel 14. Turning off the transistor 112 will create reset noise,charge injection and clock feedthrough voltage that resides across thephotodiode 100. As shown in FIG. 17 the noise reduces the voltage at thephotodetector 100 when the transistor 112 is reset.

The SAM2 line 168 is driven high, the SEL line 122 is driven low andthen high again, so that a level shifted voltage of the photodiode 100is stored as a reset output signal in the second capacitor 154 of thelight reader circuit 16. Process blocks 300 and 302 are repeated foreach pixel 14 in the array 12.

Referring to FIG. 15, in process block 304 the reset output signals arethen subtracted from the first reference output signals to create noiseoutput signals that are then converted to digital bit strings by ADC 24.The digital output data is stored within the external memory 74 inaccordance with one of the techniques described in FIG. 2, 3, 8 or 9.The noise signals correspond to the first image pixel data. Referring toFIG. 14, the subtraction process can be accomplished by closing switches182, 184 and 170 of the light reader circuit 16 (FIG. 14) to subtractthe voltage across the second capacitor 154 from the voltage across thefirst capacitor 152.

Referring to FIG. 15, in block 306 light response output signals aresampled from the pixels 14 of the pixel array 12 and stored in the lightreader circuit 16. The light response output signals correspond to theoptical image that is being detected by the image sensor 10. Referringto FIGS. 13, 14 and 16 this can be accomplished by having the IN 120,SEL 122 and SAM2 lines 168 in a high state and RST 118 in a low state.The second capacitor 152 of the light reader circuit 16 stores a levelshifted voltage of the photodiode 100 as the light response outputsignal.

Referring to FIG. 15, in block 308 a second reference output signal isthen generated in the pixels 14 and stored in the light reader circuit16. Referring to FIGS. 13, 14 and 16, this can be accomplished similarto generating and storing the first reference output signal. The RSTline 118 is first driven high and then into a tri-state. The IN line 120is then driven high to cause the transistor 112 to enter the trioderegion so that the voltage across the photodiode 100 is the voltage onIN line 120. The SEL 122 and SAM2 168 lines are then driven high tostore the second reference output voltage in the first capacitor 154 ofthe light reader circuit 16. Process blocks 306 and 308 are repeated foreach pixel 14 in the array 12.

Referring to FIG. 15, in block 310 the light response output signal issubtracted from the second reference output signal to create anormalized light response output signal. The normalized light responseoutput signal is converted into a digital bit string to createnormalized light output data that is stored in the second image buffers32 and 34. The normalized light response output signals correspond tothe second image pixel data.

Referring to FIGS. 13, 14 and 16 the subtraction process can beaccomplished by closing switches 170, 182 and 184 of the light reader 16to subtract the voltage across the first capacitor 152 from the voltageacross the second capacitor 154. The difference is then amplified byamplifier 180 and converted into a digital bit string by ADC 24 as lightresponse data.

Referring to FIG. 15, in block 312 the noise data is retrieved fromexternal memory. In block 314 the noise data is combined (subtracted)with the normalized light output data in accordance with one of thetechniques shown in FIG. 3, 4, 5, 6, 7 or 8. The noise data correspondsto the first image and the normalized light output data corresponds tothe second image. The second reference output signal is the same orapproximately the same as the first reference output signal such thatthe present technique subtracts the noise data, due to reset noise,charge injection and clock feedthrough, from the normalized lightresponse signal. This improves the signal to noise ratio of the finalimage data. The image sensor performs this noise cancellation with apixel that has only three transistor. This image sensor thus providesnoise cancellation while maintaining a relatively small pixel pitch.This process is accomplished using an external processor 72 and externalmemory 74.

The process described is performed in a sequence across the various rowsof the pixels in the pixel array 12. As shown in FIG. 16, the n-th rowin the pixel array may be generating noise signals while the n−l-th rowgenerates normalized light response signals, where l is the exposureduration in multiples of a line period.

The various control signals RST, SEL, IN, SAM1, SAM2 and SUB can begenerated in the circuit generally referred to as the row decoder 20.FIG. 18 shows an embodiment of logic to generate the IN, SEL, SAM1, SAM2and RST signals in accordance with the timing diagram of FIG. 16. Thelogic may include a plurality of comparators 350 with one inputconnected to a counter 352 and another input connected to hardwiredsignals that contain a lower count value and an upper count value. Thecounter 352 sequentially generates a count. The comparators 350 comparethe present count with the lower and upper count values. If the presentcount is between the lower and upper count values the comparators 350output a logical 1.

The comparators 350 are connected to plurality of AND gates 356 and ORgates 358. The OR gates 358 are connected to latches 360. The latches360 provide the corresponding IN, SEL, SAM1, SAM2 and RST signals. TheAND gates 356 are also connected to a mode line 364. To operate inaccordance with the timing diagram shown in FIG. 16, the mode line 364is set at a logic 1.

The latches 360 switch between a logic 0 and a logic 1 in accordancewith the logic established by the AND gates 356, OR gates 358,comparators 350 and the present count of the counter 352. For example,the hardwired signals for the comparator coupled to the IN latch maycontain a count values of 6 and a count value of 24. If the count fromthe counter is greater or equal to 6 but less than 24 the comparator 350will provide a logic 1 that will cause the IN latch 360 to output alogic 1. The lower and upper count values establish the sequence andduration of the pulses shown in FIG. 16. The mode line 364 can beswitched to a logic 0 which causes the image sensor to function in asecond mode.

The sensor 10 may have a plurality of reset RST(n) drivers 370, eachdriver 370 being connected to a row of pixels. FIGS. 19 and 20 show anexemplary driver circuit 370 and the operation of the circuit 370. Eachdriver 370 may have a pair of NOR gates 372 that are connected to theRST and SAM1 latches shown in FIG. 18. The NOR gates control the stateof a tri-state buffer 374. The tri-state buffer 374 is connected to thereset transistors in a row of pixels. The input of the tri-state bufferis connected to an AND gate 376 that is connected to the RST latch and arow enable ROWEN(n) line.

FIGS. 21 and 22 show operation of the image sensor in a second mode alsoreferred to as an extended dynamic range mode. In this mode the imageprovides a sufficient amount of optical energy so that the SNR isadequate even without the noise cancellation technique described inFIGS. 15 and 16. Although it is to be understood that the noisecancellation technique shown in FIGS. 15 and 16 can be utilized whilethe image sensor 10 is in the extended dynamic range mode. The extendeddynamic mode has both a short exposure period and a long exposureperiod. Referring to FIG. 21, in block 400 each pixel 14 is reset tostart a short exposure period. The mode of the image sensor can be setby the processor 72 to determine whether the sensor should be in the lownoise mode, or the extended dynamic range mode.

In block 402 a short exposure output signal is generated in the selectedpixel and stored in the second capacitor 154 of the light reader circuit16.

In block 404 the selected pixel is then reset. The level shifted resetvoltage of the photodiode 100 is stored in the first capacitor 152 ofthe light reader circuit 16 as a reset output signal. The short exposureoutput signal is subtracted from the reset output signal in the lightreader circuit 16. The difference between the short exposure signal andthe reset signal is converted into a binary bit string by ADC 24 andstored into the external memory 74 in accordance with one of thetechniques shown in FIG. 2, 3, 8 or 9. The short exposure datacorresponds to the first image pixel data. Then each pixel is againreset to start a long exposure period.

In block 406 the light reader circuit 16 stores a long exposure outputsignal from the pixel in the second capacitor 154. In block 408 thepixel is reset and the light reader circuit 16 stores the reset outputsignal in the first capacitor 152. The long exposure output signal issubtracted from the reset output signal, amplified and converted into abinary bit string by ADC 24 as long exposure data.

Referring to FIG. 21, in block 410 the short exposure data is retrievedfrom external memory. In block 412 the short exposure data is combinedwith the long exposure data in accordance with one of the techniquesshown in FIG. 3, 4, 5, 6, 7 or 8. The data may be combined in a numberof different manners. The external processor 72 may first analyze theimage with the long exposure data. The photodiodes may be saturated ifthe image is too bright. This would normally result in a “washed out”image. The processor 72 can process the long exposure data to determinewhether the image is washed out, if so, the processor 72 can then usethe short exposure image data. The processor 72 can also use both thelong and short exposure data to compensate for saturated portions of thedetected image.

By way of example, the image may be initially set to all zeros. Theprocessor 72 then analyzes the long exposure data. If the long exposuredata does not exceed a threshold then N least significant bits (LSB) ofthe image is replaced with all N bits of the long exposure data. If thelong exposure data does exceed the threshold then N most significantbits (MSB) of the image are replaced by all N bits of the short exposuredata. This technique increases the dynamic range by M bits, where M isthe exponential in an exposure duration ratio of long and shortexposures that is defined by the equation l=2^(M). The replaced imagemay undergo a logarithmic mapping to a final picture of N bits inaccordance with the mapping equation Y=2^(N) log₂(X)/(N+M).

FIG. 22 shows the timing of data generation and retrieval for the longand short exposure data. The reading of output signals from the pixelarray 12 overlap with the retrieval of signals from memory 74. FIG. 22shows timing of data generation and retrieval wherein a n-th row ofpixels starts a short exposure, the (n−k)-th row ends the short exposureperiod and starts the long exposure period, and the (n−k−l)-th row ofpixels ends the long exposure period. Where k is the short exposureduration in multiples of the line period, and l is the long exposureduration in multiples of the line period.

The memory controller 44 begins to retrieve short exposure data for thepixels in row (n−k−l) at the same time as the (n−k−l)-th pixel array iscompleting the long exposure period. At the beginning of a line period,the light reader circuit 16 retrieves the short exposure output signalsfrom the (n−k)-th row of the pixel array 12 as shown by the enablementof signals SAM1, SAM, SEL(n−k) and RST(n−k). The light reader circuit 16then retrieves the long exposure data of the (n−k−l)-th row.

The dual modes of the image sensor 10 can compensate for varyingbrightness in the image. When the image brightness is low the outputsignals from the pixels are relatively low. This would normally reducethe SNR of the resultant data provided by the sensor, assuming theaverage noise is relatively constant. The noise compensation schemeshown in FIGS. 15 and 16 improve the SNR of the output data so that theimage sensor provides a quality picture even when the subject image isrelatively dark. Conversely, when the subject image is too bright theextended dynamic range mode depicted in FIGS. 21 and 22 compensates forsuch brightness to provide a quality picture.

FIG. 23 a shows an alternate embodiment of an image sensor that has aprocessor bus 70′ connected to the external processor 72 and a separatememory bus 70″ connected to the external memory 74. With suchconfiguration the processor 72 may access data while the memory 74 isstoring and transferring data. This embodiment also allows for slowerclock speeds on the processor bus 70′ than the bus 68 of the embodimentshown in FIG. 1.

FIG. 23 b shows another embodiment wherein the processor 72 is coupledto a separate data interface 500 and the external memory 74 is connectedto a separate memory controller 44.

FIG. 24 shows another embodiment of an image sensor with a datainterface 500 connected to the buffers 28, 30, 32 and 34. The interface500 is connected to an external processor 72 by a processor bus 502. Inthis configuration the external memory 74 is connected to the processor72 by a separate memory bus 504. For both still images and video capturethe first and second images are provided to the external processor in aninterleaving manner.

FIG. 25 discloses an alternate embodiment of an image sensor without thebuffers 28, 30, 32 and 34. With this embodiment the ADC 24 is connecteddirectly to the external processor 72. The processor 72 may performcomputation steps such as combining (subtracting) the noise data withthe normalized light output data, or the short exposure data with thelong exposure data.

FIG. 26 discloses an external processor that contains a DMA controller510, buffer memory 512 and a image processing unit 514. The image sensor10 is connected to the DMA controller 510. The DMA controller 510 of theprocessor transfers the first and second image data to the memory 74 inan interleaved or concatenated manner. The DMA controller 510 can alsotransfer image data to the buffer memory 512 for processing by the imageprocessing unit 514.

FIG. 27 shows another embodiment of an image sensor system 550. Thesystem 550 includes an image sensor 552 that is coupled to a processor554 by a first bus 556 and a second bus 558. The processor 554 may alsobe coupled to a memory device 560 by a memory bus 562 and a non-volatilememory device 564 by a non-volatile memory bus 566.

The image sensor 552 generates a first image(s) and a second image(s).By way of example, the first image may be the digitized normalized noiseoutput signals when the system is in the low noise mode, or the shortexposure data of the extended dynamic range mode. Likewise, the secondimage may be the digitized normalized light response output signals ofthe low noise mode, or the long exposure data of the extended dynamicrange mode.

The image sensor 552 transfers the first and second images to theprocessor 554 in a time overlapping manner. The first image may betransferred across the first bus 556 while the second image istransferred across the second bus 558. It being understood that a timeoverlapping manner means that data of the second image is beingtransferred to the processor 554 while data of the first image is stillbe transmitted by the image sensor 552. By way of example, the imagesensor 552 may transfer the images to the processor by interleaving thefirst and second images on a single bus, or transferring both images ondedicated busses 556 and 558. The image sensor 552 may transfer theimage data from an internal data interface, memory controller, directlyfrom an ADC, or any other on-board processor and/or memory interface.

The processor 554 may cause the first image to be stored in the memorydevice 560 and then later recombined with the second image.Alternatively, the memory device 560 may store the entire first andsecond images. The first and second images may then be retrieved andcombined by the processor 554. As yet another alternative, the memorydevice 560 may store only a portion of the second image.

The non-volatile memory device 564 may be a read only memory (“ROM”)that contains embedded firmware. The firmware may include a program thatcauses the processor 554 to receive the first and second images in atime overlapping manner. By way of example, the program may cause theprocessor 554 to receive the images in an interleaved manner.Alternatively, the processor 554 may be configured to have a combinationof firmware and hardware, or a pure hardware implementation forreceiving the image data in a time overlapping manner.

As shown in FIG. 28, the processor 554 of the dual bus system 550 maycontain an on-board DMA controller 566, a buffer memory 568 andprocessing unit 570 similar to the processor shown in FIG. 26. The DMAcontroller 566 may cause the image data to be stored and retrieved fromthe memory device 560.

FIG. 29 shows an embodiment of a dual port DMA controller 566 that has aplurality of buffers 572, 574, 576 and 578. Buffers 572 and 574, and 576and 578 are coupled to the busses 556 and 558 by switches 580 and 582,respectively. The buffers 572 and 574, and 576 and 578 are coupled tothe memory bus 562 by switches 584, 586 and 588. The buffers andswitches may operate similar to the buffers 28, 30, 32 and 34, andswitches 38, 40, 42, 48 and 54 of the image sensor shown in FIG. 1.

The DMA controller 566 may have a logic circuit 590 that causes thefirst image data to be stored in buffers 572 and 574 and the secondimage data to be stored in buffers 576 and 578. Buffers 574 and 578 maystore data from the busses 556 and 558, respectively, while the memorydevice 560 stores first image data and second image data from buffers572 and 576, respectively. Buffers 572 and 576 may then store data frombusses 556 and 558 while buffers 574 and 578 provide data to memory 560.The buffers 572, 574, 576 and 578 may alternate between storing datafrom the busses 556 and 558 and providing data to the memory device 560.The DMA controller 566 can control the memory location of the image datawithin the memory device 560.

Although not shown, the image sensor systems shown in FIGS. 23 a, 23 band 25 may also have a dual bus arrangement. The embodiments shown inFIGS. 23 a and 23 b may have dual busses for the processor 72 and/ormemory 74.

It is the intention of the inventor that only claims which contain theterm “means” shall be construed under 35 U.S.C. §112, sixth paragraph.

While certain exemplary embodiments have been described and shown in theaccompanying drawings, it is to be understood that such embodiments aremerely illustrative of and not restrictive on the broad invention, andthat this invention not be limited to the specific constructions andarrangements shown and described, since various other modifications mayoccur to those ordinarily skilled in the art.

For example, although interleaving techniques involving entire lines ofan image are shown and described, it is to be understood that the datamay be interleaved in a manner that involves less than a full line, ormore than one line. By way of example, one-half of the first line ofimage A may be transferred, followed by one-half of the first line ofimage B, followed by the second-half of the first line of image A, andso forth and so on. Likewise, the first two lines of image A may betransferred, followed by the first two lines of image B, followed by thethird and, fourth lines of image A, and so forth and so on.

Additionally, the processor 72 and/or 554 may be a digital signalprocessor provided by Texas Instruments under the part designationTMS320DSC21, TMS320DSC25, TMS320DM270 or TMS320DM310, or a modifiedversion of these parts.

1. An image capture apparatus, comprising: a pixel array that generatesa first image and a second image in a time-overlapping manner; a busacross which the first image and the second image are transmitted in atime overlapping manner such that a transmission of the second imagebegins before a transmission of the first image is terminated; and aprocessor that is coupled to said pixel array across said bus, saidprocessor receives the first and second images transmitted across saidbus, the first image starts transmitting before the second image, thesecond image starts transmitting before the first image terminates itsfirst-time ever transmission across said bus.
 2. The image captureapparatus of claim 1, wherein the first and second images are stored intwo different buffer areas in said processor.